Nanomaterials Certificate Georgia Tech

Georgia Tech Packaging Research Center e-Newsletter


The Packaging Research Center (PRC) has begun its transition from NSF-centric to Global Industry-centric. Over the last 11 years, the PRC has been a National Science Foundation engineering research center focusing on an integrated approach to Research, Education and Industry Collaboration in the SOP technology paradigm. During this period, it pioneered SOP technology, developed extensive expertise, facilities and collaborated with more than 150 companies around the globe, transferring parts of SOP technologies to them. It also made Packaging an academic subject for the first time, with courses, curricula and textbooks, and graduated over 575 students.

The PRC transition is taking place in research with newer emerging technologies such as embedded actives and passives, nano-bio-info technologies, and in research staff to address these newer technologies and to work with industry more effectively.

The PRC is now very Industry-centric and Global. It works with global industry in exploring newer technologies at project level, and in addition, it is setting up large thematic, program level consortia on a variety of topics. The PRC is in the process of launching two consortia titled "Embedded Actives and Passives (EMAP)" and "Mixed Signal Design Tools (MSDT)". The PRC is currently working on three other consortia in the areas of Thermal Interface Materials (TIM), Electrical Test and Fault Tolerance (ETFT) and Nano-materials, Components, Packaging and Systems (NanoPack). Plans for future consortia include Design for Signal and Power Integrity, Wafer Level SOP, RF SOP, and Opto SOP.

Given its breadth of know-how from Design to Prototype, on one hand, and complete cleanroom facilities on the other hand, it is also embarking on large company contracts to demonstrate the next generation of SOP-based modules.

PRC views the participation of students to be a very important component of research and education. PRC has therefore set up a student council with Todd Spencer as president. Todd, along with the student steering committee consisting of Prof. Madhavan Swaminathan and five graduate students oversee the functioning of the PRC student body by arranging distinguished lecturer seminars, managing the IEEE CPMT Society's student chapter, ensuring interaction between faculty and students, and managing student recruitment activities.

The PRC now has a fully functional management team with Prof. Madhavan Swaminathan as Deputy Director, Dr. Mahadevan Iyer as Research Director, Dean Sutter as Finance and Infrastructure Director and three Assistant Research Directors: Dr. Raj Pulugurtha, Dr. Chong Yoon and Venky Sundaram. In addition, the faculty continue to lead the research areas such as Prof. Swaminathan for SOP Design, Prof. John Papapolymerou for RF SOP, Prof. Gee-Kung Chang for Opto SOP, Prof. C. P. Wong for Wafer Level Packaging and Assembly.

Prof. Rao R. Tummala
Endowed Chair Professor
Director of PRC, Georgia Tech



Electrical Test & Fault Tolerance (ETFT)
A workshop for starting an industry-academia consortium on Electrical Test and Fault Tolerance (ETFT) is now set for November 7th, 2006 at the Georgia Tech PRC. Details are posted on the PRC website: This consortium focuses on approaches to solve the problems in electrical test and fault tolerance as it applies to manufacturing of mixed signal systems and packages. From the workshop, a preliminary list of projects will be proposed, selected, and further refined as the consortium is launched based on inputs from industry. A launch meeting is planned for March 2007 and the launch date is expected in July 2007. For more information, please

Nano Materials, Components, Packaging and Systems(NanoPack)
Nano-science and technology has been a buzzword for about five years. Most of the research to date in this area, however, has been focused either in materials or devices. Such technologies as carbon nano tubes (CNTs), molecular self assembly and manufacturing, nano imprints, etc., are being explored and studied for mechanical, physical, chemical, photonic, electronic and biological properties. The Packaging Research Center proposes to go beyond nano-materials and devices to form chip-to-package interconnections, components, sensors, dielectrics, coatings and batteries leading to nano-modules. This proposed emphasis is expected to lead to a number of commercial applications, not achieved so far. To accomplish these goals, the Packaging Research Center proposes a global Industry-Academia consortium on "Nano Materials, Components, Packaging and Systems (NanoPack)" to explore a variety of new opportunities that these materials may provide.

The first "NanoPack" workshop will be held March 16, 2007 at the Georgia Tech Packaging Research Center, Manufacturing Research Center (MaRC) auditorium.
Encouraged to attend are executives and engineers from electronics, energy, biotech/pharma, and defense/aerospace industries; experts from semiconductor equipment, metrology and material industries interested in capitalizing on nanotech opportunities; entrepreneurs committed to exploring viable new nano manufacturing technologies,


Thermal Interface Materials (TIM)
The TIM consortium workshop was held on September 27th, 2006 at the Georgia Tech PRC, with more than 50 attendees from industry and academia. This workshop was intended to form an industry-academia TIM consortium led by GT-PRC which enables to address and solve core research problems in the area. There were 5 presentations from industry such as IBM, Honeywell, Intel, GE and Rockwell-Collins and 6 presentations from GT-PRC and University of Binghamton. At the end of the workshop, 12 key projects ranging from various thermal interface materials, characterization, validation, thermal modeling, interfaces and reliability were proposed and reviewed by industry and academia. The consortium is expected to start April 2007. Interested

Mixed Signal Design Tools (MSDT) - Ready for LaunchFocus on Next Generation EDA for Integrated Microsystems

The focus of this consortium is the development of next generation design tools that enable the deployment of SiP (System in Package) and SoP (System on Package) technologies. Based on a pre-launch meeting held in June ’06 and follow-on meetings with industry, the MSDT consortium will focus on the following projects:

  • Power Ground Network Simulator and Optimizer
  • Design for Manufacturing (DFM) Methods for SiP
  • Automated Methods for the Design of Embedded Passives
  • Early Exploratory Tool for Chip-Package Co-Design
  • EBG Modeling and Synthesis
  • Modeling of Coupling in 3D Integration
  • Parametric models of Linear 3D Electrical Interconnects and Packages (EIP)

The last project is in collaboration with Polytechnico Di Torino, Italy. Along with providing rapid analysis capability, these tools are expected to support both design and verification. Interfaces to commercial tools have been planned as part of the consortium activities.The duration of the consortium is two years.
Companies interested in joining the consortium are encouraged to

Embedded Actives & Passives (EMAP)
PRC to Launch Embedded Module with Ultra-thin Active and Passive Components (EMAP) Consortium Focusing on Next Generation Mixed Signal System Modules for Wireless and Mobile Product Applications
The focus of this consortium is to go beyond SIP technology development underway around the world by further miniaturization technologies at IC, module and system levels. The design and fabrication of ultra thin embedded active and passive components will be accomplished in the EMAP consortium. The initial major emphasis of the EMAP consortium is on mobile product applications with focus on RF/wireless modules/packaging, and baseband processor packaging for cellular, WLAN, WiMAX and other wireless communication systems. Based on a pre-launch meeting held in June ’06 and follow-up meetings with industry, the EMAP consortium will be launched with the following tasks and research projects:

  • EMAP Design and Characterization
  • Ultra Thin Substrate: Thin Core Substrates, Low Loss Build-up Dielectric Materials and Processes, and Embedded Actives in Substrate Cavity
  • Ultra Thin Silicon Die: Wafer Thinning and Dicing, Handling, Characterization and Drop Impact Studies
  • Thermal Management: Advanced Passive Cooling Technologies
  • Embedded RF MEMS Switch
  • Chip-Last Die-to-Package Interconnection: Chip-last with Cu Bump with or without Reworkability and Chip-last Approach Device Attachment Using Self-Assembly Processes

The two Ultra-thin Silicon projects and the self-assembly project will be undertaken in collaboration with the Institute of Microelectronics (IME), Singapore. These enabling technology building blocks are expected to enable future SiP and SOP modules with reduced thickness and form factor. Along with several global RF/digital semiconductor suppliers and OEMs for wireless applications, materials suppliers, tool suppliers, fabricators, and other supply chain companies will be participating in the consortium to provide a viable commercialization path for the new technologies. The duration of the first phase of the consortium is two years.

Companies interested in joining the consortia are encouraged to contact Venky development workshops, please visit: INNOVATIONS

Embedded Sensors with SOP
PRC has renewed its second-year contract of its five-year program on embedded sensors for defense and security applications. This effort is carried out under a co-operative research agreement with the Sensors and Electron Devices Directorate of the Army Research Labs (ARL) in collaboration with the Army Natick Soldier Center. Southwest Research Institute will integrate the effort of the team which includes, Syracuse University, Albany Nanotech (University at Albany) and PRC, with its primary partner, Starfire Systems, Inc. The goal of this project is to demonstrate an ultra-microminiaturized megafunction system that will enable the integration and combination of multiple sensors, control logic, wireless interfaces, and embedded power sources into a robust silicon carbide board based substrate.

The first year effort focused on demonstrating some of the principal component technologies to fabricate the miniaturized temperature and humidity sensor on the novel Carbon fiber reinforced-SiC substrate. A system package with thin film embedded resistors (1000 ohms/square) and capacitors (500 nF/cm2), fine line wiring on ultra low loss build-up dielectrics was fabricated on the C-SiC substrate at PRC to demonstrate the prototype. In the second year, the SMT sensors will be upgraded to integrated thin film sensors with increased number of sensors per patch. The RC component technologies will be further enhanced to meet the microcontroller and power regulation requirements of the new sensor arrays with the incorporation of wireless sensing capabilities and embedded power sources. The wearable electronics technologies developed under this program are expected to be spiraled out for commercialization in consultation more details about this program).

PRC Demonstrates Protein and Cancer Cell Sensing with Nanostructured Oxides
PRC recently started to explore nanostructured oxide materials for their biosensing characteristics. Certain semiconducting oxides are widely known and commercially applied for their gas sensing properties. However, biochemical sensing has mostly depended on optical and electrochemical techniques that are more cumbersome. Recent experimental results from the nanobiosensing group at PRC indicate that even the conductimetric properties of nano and thin film oxides can be sensitized to protein and cancer cell hybridization reactions and can be accurately detected. Nano zinc oxide sensors showed significant changes in conductivity after protein functionalization with rabbit IgG and hybridization with anti-rabbit IgG. Systematic changes in conductivity of nanosensors were also measured after coating the oxides with cancer cells. This biosensor has potential for early detection of prostate-specific antigen (PSA) and breast cancer genes such as HER2 (or HER2/neu), BRCA1 and BRCA2 I. Contacts: Dr. Janagama

Miniaturization of Wireless with Magnetic Nanomaterials
Since its beginning, PRC has underscored the need for novel nanomaterials with superior magnetic and dielectric properties to achieve miniaturized components. Based on some of the bottom-up chemical processing methods, new magnetic nanocomposites can be synthesized with higher permeability at high frequencies, lower losses, higher magnetization leading to tremendous benefits in size and weight reduction coupled with superior performance. PRC integrated novel magnetic nanocomposites in organic substrates for embedded power converters, in collaboration with its partner Inframat Corporation, as a part of a NSF contract. While most bulk magnetic materials show lower permeability in MHz frequencies, this new material is shown to retain higher permeability up to GHz frequency.

These materials are now being further enhanced to evaluate their suitability for the emerging wireless applications. Because of their higher permittivity and permeability, an order of magnitude reduction in size can be achieved for wireless components without the traditional disadvantages such as domain wall resonances, hysteresis losses and eddy current losses that come with microstructured ferroic materials. In addition, good impedance match can be expected for wireless interfaces because of the matching permittivity and permeability. The performance is expected to improve further as we take advantage of the recent advances in nanotechnology. PRC is now partnering with leading system companies in exploiting the true benefits of magnetic nanocomposites. Contact: Dr. Raj Pulugurtha

Methods for Analysis of Signal and Power Integrity for Advanced Packaging
PRC has been developing design tools and methodologies for advanced packaging that support mixed-signal and high-performance circuits for more than a decade. The goal of this activity has been to develop a comprehensive tool-set to reduce design cycle time.

Any analysis method can only be as accurate as the input provided by the user. For signal integrity analysis using electromagnetic (EM) solvers, this is mainly the geometrical features and the material properties. Dielectric constant and loss tangent given at 1MHz, which is the common practice today, are not sufficient for accurate analysis of high-speed signals. At PRC, we have developed a method to extract the frequency-dependent dielectric constant and loss tangent of substrate materials using rectangular power/ground planes. This provides a simple method combined with a new rapid plane solver for fast extraction of material properties from such measurements.

For EM analysis, we have developed a tool based on the Multilayered Finite-Difference Method (M-FDM) that can simulate realistic packages and boards with arbitrary number of layers. M-FDM can be 2-3 orders of magnitude faster than full-wave solvers with comparable accuracy for planar structures by including second-order effects such as edge and gap fields.

For system-level signal integrity simulation, we have developed a new method that combines frequency-domain data in a modified nodal analysis (MNA) framework. This method also ensures causality of the system response, which is unique in time-domain simulators. This method has been successfully applied to distributed networks such as transmission lines and power ground planes. Contact: Dr. Ege Engin

Recent Advances in Thermal Management Research
Recent research in the thermal management group has been focused towards laying the foundation for the EMAP consortium. This includes basic estimates of the performance of handheld cooling devices. Other work from Prof. Joshi and Dr. David Gerlach deals with 3D stacked chip electronics cooling by conduction spreaders. In addition, subambient (-100ºC) cooling with cascade vapor compression cycles and heat-driven adsorption cycles have been researched. A new pattern for branching flow channels has been developed for the interstage heat exchanger of the cascade system. This pattern can also be easily mapped to a square for cooling dies. Contact:

Solder Joint Fatigue Life Estimation Using Laser Moire Interferometry
Laser moiré interferometry has been traditionally used for determining deformation contours and/or strain contours in solder joints, and such contours have been used to determine critical solder joints as well as to validate the deformation contours obtained through numerical modeling. In this ongoing project, we have used the laser moiré interferometry to identify critical solder joints and to predict the number of cycles to fatigue failure. The proposed approach is being implemented for PBGA and CBGA packages for different thermal cycling regimes (-55 to 125 °C, 0 to 100 °C, etc.). Unlike the experimental accelerated thermal cycling that takes several months to determine the fatigue life, the laser moiré-based prediction takes less than one week to complete, and at the same time, may not suffer from the modeling assumptions that are seen in numerical predictions. For additional information, please contact Prof. Suresh Sitaraman


New Company Memberships
LG Electronics: Joined Wafer Level Packaging alliance in Sept. 2006
Rogers Corporation: Joined SOP alliance in Sept. 2006

Renewed Company Contracts

  • Starfire: “Functionally Integrated Reactive Surface Technologies, ” year 2 of 5, Prof. Rao Tummala and Dr. Raj Pulugurtha
  • National Semiconductor: "Design of Load Boards with EBG for ADC Testing, " GT Foundation grant, Prof. Madhavan Swaminathan
  • “Dutchess" Project: Two-year contract extended for additional six months from Oct. 2006 to March 2007, Prof. Rao Tummala
  • NASA: "Large, lightweight deployable arrays using RF MEMS Switches, " Oct. 2006 to Oct. 2007, Prof. John Papapolymerou
  • NSF: "Fundamental Understanding of Nanofiller Dispersion in Polymer Systems for Electronics Applications, " 2006 to 2009, Prof. C. P. Wong


U.S. Patent Title: "Ultra-High Capacitance Densities with 3D Capacitors" - Simple thin film capacitors can only yield limited capacitance densities of about 5 µF/cm2. This capacitance density cannot keep up with the increased demands of high performance mixed signal system integration and miniaturization. To get much higher capacitance densities, it is important to utilize the third dimension for generating high surface area electrodes so that the capacitor volume can be more efficiently utilized. Semiconductor companies have invented trench capacitors for DRAM and other applications many years ago and are now pursuing this direction for other decoupling and charge-storage applications. PRC recently filed a patent on organic and WLSOP compatible 3D capacitors with micro and nanostructured electrodes. Based on high surface area base metal electrodes, co-processing of metal with sol-gel and other novel chemical processing routes to deposit high k ceramic thin films, this technology is expected to provide more than 20 µF/cm2 without sacrificing the resistance, high-frequency performance and other attributes such as low leakage current and sufficient Break Down Voltages (BDV) required for decoupling at GHz frequencies. This technique can also be extended to nanostructured electrodes and novel thin film conformal coating leading to much higher capacitance densities (100 µF/cm2).

Tweaking solar cells w/quantum dots

by Citizen_J

Potential 45% increase in efficiency
Researchers from the University at Buffalo, Army Research Laboratory and Air Force Office of Scientific Research have developed a new, nanomaterials-based technology that has the potential to increase the efficiency of photovoltaic cells up to 45 percent. Specifically, the researchers have shown that embedding charged quantum dots into solar cells can improve electrical output by enabling the cells to harvest infrared light, and by increasing the lifetime of photoelectrons

Contrast Media/Contrast Agents Market (Radiology, Interventional Radiology ..  — PR Web

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